This article discussed the latest developments of RISC-V computing for storage applications based upon presentations at the 2020 RISC-V Summit as well as Marvell Technologies advances in storage controllers, NICs and preamps to support customized SSDs, Ethernet Bunch of Flash and advanced nearline HDDs.

Reduced Instruction Set Computing (RISC) is a computer architecture that has instructions that can be executed in one computer clock cycle.  Multiple instructions are often needed to complete a given task.  Complex Instruction Set Computing (CISC) completes a task in as few lines of software code as possible, thus using complex instructions that may take multiple computer clock cycles to complete.  RISC offers advantages in terms of less complex computing hardware and enabling pipelining (out-of-order command execution).  RISC was originally introduced in the 1970’s, but it took a long time to get commercial acceptance due to a lack of software support.  The Intel X86 is one of the few chips which retain the CISC architecture.

RISC-V is an open and free RISC instruction set architecture.  The RISC-V community is promoting the use of RISC-V processors, hardware and software.  At the recent RISC-V Summit there were talks by Western Digital and Seagate on their use of RISC-V processors in their storage devices and systems.

Western Digital has been a long time supporter of RISC-V and in 2017 announced its intent to moving all of its processors used in HDDs, SSDs and storage systems to RISC-V.   In 2020 the company has RISC-V cores and innovations as well as tools and resources to support its RISC-V efforts.  The company’s SweRV core in its controller SoC interfaces directly with NAND flash memory as well as SATA or PCIe (NVMe) hosts.  The image below shows WDC’s SweRV core enabled controller in an SSD.

The SweRV core has been adopted by several semiconductor organizations, including a large GPU company.  At WDC the company has two varieties of SweRV cores.  The first is the EH2, which is a cual-threaded embedded RISC-V core that enables significant random read IOPS with a single core.  The second is the EL2, a low power small 4-stage core customized for sequencer and state machines.  Both of the devices are available for download from Github through the Chips Alliance.  These RISC-V cores offer performance on core with some of the best core IP on the market.

Another WDC RISC-V solution is their OmniXtend that allows sharing of main memory with a fast open coherency bus between various types of processors as shown below.

Seagate also spoke at the RISC-V Summit and announced its use of RISC V cores for real-time processing of motion control information for HDD head positioning.  As Seagate and other HDD companies increase their storage capacities by 50TB and beyond (resulting in over 1 million tracks per inch with 2.4nm positioning accuracy) and implementing multi-stage actuators to increase the IOPS per TB they need sophisticated real time processing.  This processing is used to position the heads involve disturbance detection, adaptive control, feed-forward compensation and high sample-rate computation.  A high-performance RISC-V core was developed by Seagate to do this real-time motion control processing as shown below.

Seagate also is looking at RISC-V used for its Open Titan root of trust to provide data trust worthiness at the edge.  The company has also designed an area optimized RISC-V core for this application as will as other auxiliary workloads.  The company was showing an OpenTitan root of trust protype using an FPGA during the summit.

At recent conferences and at a Marvell Analyst Day in December, the company gave a view of developments in its digital storage products.  Marvell is a major supplier of controllers for hard disk drives (HDDs) and solid state drives (SDDs) as well as storage networking products.  These announcements will help increase the storage contribution to Marvell’s revenue.

Networking is a key element in storage systems, in particular, as will be made clear below, Ethernet networking is a major driver of digital storage system advances to meet storage management and processing needs.  Among the storage-oriented technologies Marvell discussed at the analyst day are their Data Processor Units (DPUs) storage accelerators, new NVMe and NVMe over fabric support, Ethernet Bunch of Flash and the Do-it-yourself SSD.  They are also supplying preamps and controllers for the next generation of HDDs using energy assisted magnetic recording.

The figure below shows Marvell’s Do-it-yourself SSD.  The idea is to enable customized SSDs for particular applications, such as the at the edge or in data centers.

Storage accelerators are special purpose processors that are located close to or in a digital storage device and which off-load some operations from the system CPU, resulting in faster performance and lower latency.  Marvell’s 480GB RAID 1 Boot SSD isolates and protects boot/recovery versus user data and can be an important element in creating virtualized infrastructure without CPU involvement.  The hypervisor runs on the accelerator rather than the system CPU allowing direct access of virtual machines to SSD storage, improving NVMe performance and lowering latency.

Marvell also talked about its Ethernet Bunch of Flash (EBOF), which the company had demonstrated with Kioxia earlier in 2020.  This is enabled by a special SSD controller that provides native NVMe-over Fabric (NVMe-oF) Ethernet SSDs.  Using Ethernet connectivity, it allows end to end multipath data movement and simple daisy chain expansion.  

The company said that EBOF storage systems are now available from ODM systems companies ingrasys (part of FOXCONN) and Accton.  These systems have options for Ethernet native SSDs as well as Ethernet connectivity through an interposer card and offering up to 84GB/s performance with 21M 4K IOPS as shown below.  The products include Marvell’s Prestera switch products for congestion management.

These EBOF flash products had a 3X throughput improvement compared to traditional Just a Bunch of Flash (JBOF) products, when tested at Los Alamos National Laboratory and can offer a 4X improvement and 72% lower latency when used for AI/ML workloads using NVIDIA GPUDirect Storage (with an NVIDIA DGX A100).

Marvell has also had its own Data Processing Unit (DPU), an accelerator technology for data center workloads called OCTEON, which has evolved since its introduction in 2005.  Marvell said that modern data centers will use CPUs, GPUs and DPUs, with DPUs handling traffic management, virtual switching, security processing, be a root of trust as well as provide storage virtualization and data compression.  Data center workloads are moving from application centric to data centric, favoring DPU processing.

The company also supports storage devices for semi-autonomous and self-driving cars.  The amount of data that these cars are estimated to generate is about 4.2TB, from cameras and other sensors on the vehicle.  Marvell said that it had made progress on automotive SW-centric, centralized and modular zonal automotive compute architectures using an Ethernet backbone.  Marvell contributed to this centralized compute environment with its OCTEON based automotive DPU that offered general purpose computing, data processing (including storage management), AI processing and security processing.  Centralized storage would use NVMe SSDs or eventually NVMe Ethernet SSDs.

Marvell is also a major supplier of HDD controllers and preamp (electronics for writing and reading data from a hard disk drive head located inside the HDD on the drive head tack).  In the last few years, the growth in storage capacity of HDDs for nearline data center applications has shown fairly slow growth due to limits on the areal density increases possible with conventional perpendicular recording and limitations in the number of disks in the drives.  With the introduction of energy assisted magnetic recording HDDs in 2020-21 and perhaps with increasing number of disks in HDDs (currently no more than 10 but perhaps up to 11 or 12 disks in the future) higher capacity HDDs will be possible.  

The figure below, from Marvell’s presentation, shows that 30TB HDDs may come in 2023 with 50TB HDDs by 2026.  By continuing to offer higher capacity HDDs the HDD companies can continue to have a cost advantage per TB compared to SSDs.

Marvell said that it is working with the HDD companies to enable increasing IOPS/GB using multi-actuator HDD technology and that with more disks per drive it is increasing the number of preamp channels needed to support the extra heads, as well as enabling energy-assisted recording in the write elements.  Marvell has also demonstrated NVMe HDDs, first using anb interposer from SATA to Ethernet (at the OCP Tech Week in November 2020).  With the increasing use of NVMe it is clear that it has become the dominate storage interface.  

Being able to manage HDDs as well as SSDs with the same storage protocols will allow mixing HDDs and SSDs in a single shelf using PCIe and also allow HDDs to benefit from SSD accelerators designed for PCIe.  This would make NVMe a universal language for SSDs, storage class memories (SCM, or Persistent Memories, PMs) as well as HDDs and reduce the overhead for storage driver maintenance.

Marvell’s Analyst Day presentations showed the company’s commitment to storage management and networking.  Their semiconductor products enable customized SSDs, universal NVMe over Fabric connectivity, including with HDDs, and enable DPU accelerator-based solutions for storage management from autonomous automobiles and IOT applications to data centers.

RISC-V WDC and Seagate advances will enable new generations of storage products and shared memory. Marvell announced DIY SSDs, EBOF and advanced HDD products. These advances enable the next generation of storage.